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P. G. DIPLOMA IN VLSI DESIGN
Bit Mapper - VLSI Design & Training
Next Batch Commencing From : June 11 2006
Bit Mapper - VLSI Design & Training
June 11 2006
Bit Mapper - VLSI Design & Training
Modules
Bit Mapper - VLSI Design & Training
  • DIGITAL DESIGN ASPECTS
  • INTRODUCTION TO VLSI
  • DESIGNING USING VHDL
  • SIMULATION ISSUES
  • SYNTHESIS ISSUES.
  • TIMING ISSUES.
  • FINITE STATE MACHINE.
  • SPECIAL CIRCUITS
  • PLD ARCHITECTURE
  • FPGA BACKEND
  • CMOS VLSI
  • VERIFICATION USING HDLs
  • MEMORY & ITS COMPONENTS
  • DIGITAL SIGNAL PROCESSING
  • PERIPHERAL COMPONENT INTERCONNECT [PCI]
  • DESIGN FOR TESTABILITY
  • FINAL PROJECT.
Bit Mapper - VLSI Design & Training
Course Details
Bit Mapper - VLSI Design & Training
Total Course Duration: 24 weeks ( 6 Months )
Bit Mapper - VLSI Design & Training
Theory Days: 20 Weeks. ( 5 Months ).
  • Theory : 180 Hours. (Daily 1 ½ Hours)
  • Lectures on Digital : 90 hours (1 ½ hours for 3 days in a week)
  • Open forum on Placements: 30 Hours (1 ½ Hour once a week)
  • Guest Lectures & Seminars : 10 Hours.
Total Theory Hours: 310
Bit Mapper - VLSI Design & Training
Lab Days: 24 Weeks ( 6 Months)
  • Lab hours: 360 (2 ½ Hours Daily)
  • Extra lab Hours: 288 ( 2 Hours Daily)
Total Lab hours: 650
Bit Mapper - VLSI Design & Training
Project Work
Bit Mapper - VLSI Design & Training
4 weeks (1 Month )
Bit Mapper - VLSI Design & Training
Eligibility
Bit Mapper - VLSI Design & Training
  • B.E. ( Electronics, Computers or Equivalent )
  • M.Sc. ( Electronics )
Selection will be based on entrance test followed by an interview
Bit Mapper - VLSI Design & Training
  • Will be an On-Line Test based on the following topics, viz.
    Fundamentals of Electronics, Analog and Digital circuits, Microprocessor
    Architecture and Memory Interfaces, Computer Awareness, General Aptitude.
  • All questions will be of Multiple Choice Objective types.
  • Students can prepare for the test by referring to their Graduate Level Text Books and notes.
  • Admission will be strictly based on Entrance test and Interview and confirmed on first come first serve.
Duration of Test: 1-Hour.
Test Timing: There are no fixed timings. Students can book their test times with the counsellor in advance and appear for the test at the fixed time and date at our institute, Pune.
Bit Mapper - VLSI Design & Training
Interview
Will be based on the test given by the student. Interviews of successful candidates will be conducted immediately after the Test.

A selected student have to submit the following documents:
  • Xerox Mark sheet of B.E.
  • Two-passport size photograph.
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Bit Mapper - VLSI Design & Training
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